1. Field of the Invention
The present invention relates in general to a phase-change memory device and a method of manufacturing the phase-change memory device.
2. Description of the Related Art
As information technology rapidly develops, semiconductor devices having substantially high response speed, substantially large storage capacity and substantially low power consumption are desired for portable communication devices designed to process a substantial amount of data. For example, these semiconductor devices may have the high response speed of a static random access memory (SRAM) device, non-volatile characteristics of a flash memory device, and high integration degree of a dynamic random access memory (DRAM) device, even though the semiconductor device may operate with low power consumption than a SRAM, flash memory and/or DRAM device.
Recently, research has begun in earnest into developing memory devices such as a ferroelectric random access memory (FRAM) device, a magnetic random access memory (MRAM) device, a phase-change random access memory (PRAM) device and nano-floating gate memory (NFGM) device, since these memory devices may operate with substantially lower power consumption and may exhibit desired characteristics as related to writing data thereto, reading data therefrom and maintaining data therein. Among those memory devices, attention from a development and/or research perspective has become focused on the PRAM device, because the PRAM device has a relatively high degree of integration and high response speed, etc., while having a relatively simple construction. Additionally, the PRAM device may be manufactured at a relatively lower cost as compared to other memory devices.
A phase-change memory device may include phase-change material having a crystalline structure that may vary in accordance with a heat generated by a current applied to the phase-change material. Phase-change material employed for the phase-change memory device may includes a chalcogenide material or alloy, for example, such as germanium-antimony-tellurium (Ge—Sb—Te, also referred to as ‘GST’). Phase-change material such as GST has a crystalline structure that varies according to a heat caused by an amount and time of a current applied thereto. In general, amorphous GST has a relatively high specific resistance, whereas crystalline GST has a relatively low specific resistance. Due to the resistance variation properties of GST, a phase-change memory device including GST may store data therein.
FIG. 1 is a cross-sectional view illustrating a conventional phase-change memory device. Referring to FIG. 1, the conventional phase-change memory device includes a data store element 47 in an active region of a semiconductor substrate 1 that has an isolation layer 3 thereon to define the active region. Word lines 5 are provided on the semiconductor substrate 1, with a first contact region 7 and a second contact region 9 provided at surface portions of the semiconductor substrate 1 between the word lines 5.
A lower insulating interlayer 21 may include a first insulating interlayer 11 and a second insulating interlayer 19 on the semiconductor substrate 1. A first contact hole 23 may be formed through the lower insulating interlayer 21 to expose the first contact region 7. A storage plug 27 including a first plug 13 and a second plug 25 may be provided in the first contact hole 23. The first plug 13 may be connected to the first contact region 7 and the second plug 25 may be positioned on the first plug 13, as shown in FIG. 1.
A bit line pad 15 contacting the second contact region 9 may be provided through first insulating interlayer 11, with a bit line 17 provided on the bit line pad 15. The second insulating interlayer 19 may be formed on the semiconductor substrate 1 with the bit line 17 formed thereon.
The data store element 47 may be formed on the second insulating interlayer 19 of lower insulating interlayer 21. The data store element 47 may include a first barrier layer pattern 29, a phase-change layer pattern 31 and a protection oxide layer pattern 33. The phase-change layer pattern 31 may be formed of a phase-change material that has two stable phases according to a temperature variation thereof, such as GST, for example. The first barrier layer pattern 29 may be formed of a metal nitride so as not to react with the phase-change layer pattern 31. To prevent an oxidation of the phase-change layer pattern 31, the protection oxide layer pattern 33 may be formed with one of a silicon nitride, boron nitride, silicon carbide or zinc sulfide.
An upper insulating interlayer 35 covers the data store element 47, and a plate electrode contact hole 37 may be formed through the upper insulating interlayer 35 to expose the phase-change layer pattern 31 of the data store element 47. A spacer 39 is provided on an inside of the plate electrode contact hole 37. A second barrier layer pattern 41 of metal nitride may be formed on the upper insulating interlayer 35 to fill the plate electrode contact hole 37. A plate electrode 43 may be formed on the second barrier layer pattern 41.
To write data to the data store element 47 of FIG. 1, a portion of the phase-change layer pattern 31 in contact with the second barrier layer pattern 41 may be converted into a crystalline or amorphous state, as shown FIG. 2A, when a current is applied to the phase-change layer pattern 31 so as to generate heat therein.
The conventional phase-change memory device has a vertical construction in which the first barrier layer pattern 29, phase-change layer pattern 31, second barrier layer pattern 41 and plate electrode 43 are vertically stacked on the semiconductor substrate 1. In this conventional phase-change memory device with vertical construction, a phase-change region generated in a phase-change layer pattern 31 is substantially small. This is because the phase-change region may be formed only at a portion of the phase-change layer pattern 31 that is in contact with an electrode (such as plate electrode 43 via second barrier layer pattern 41). In addition, a relatively high current is applied to the phase-change layer pattern 31 from the electrode so as to generate heat for sufficiently forming phase-change region in the phase-change layer pattern 31. This problem is described in further detail with reference to FIGS. 2A and 2B.
FIG. 2A is a schematic cross-sectional view illustrating the phase-change region of the conventional phase-change memory device of FIG. 1; and FIG. 2B is a schematic cross-sectional view illustrating a temperature distribution of the conventional phase-change memory device of FIG. 1. In FIG. 2B, the temperature distribution of the conventional phase-change memory device is a simulated result obtained using CFD-ACE+ program provided by CFDRC Co. in U.S.A.
Referring to FIGS. 2A and 2B, in the conventional phase-change memory device with vertical construction as shown in FIG. 1, a phase-change region 55 is formed only at a minute portion of a phase-change layer 53 that is in contact with a contact 51 (such as an electrode). Since heat causing specific resistance variation of the phase-change region 55 depends on current applied to the phase-change layer 53 from contact 51, the heat is generated in the phase-change layer 53 centering around an interface between the phase-change layer 53 and the contact 51. That is, a temperature distribution Td causes the heat generated in the phase-change 53 to lean to the contact 51 centering the interface between the phase-change layer 53 and the contact 51 as shown in FIG. 2B. Thus, the heat generated in the phase-change region 55 may be dissipated through the contact 51, because the contact 51 (which may be a metal or a metal nitride, for example) has thermal conductivity about seven (7) times larger than that of the phase-change layer 53 (which may be GST).
As heat dissipation occurs in the phase-change layer 53, more heat is thus required to generate the phase-change region 55 in the phase-change layer 53 so that relatively high reset current is applied to the phase-change layer 53 from the contact 51 (a reset current is applied as part of a reset operation to change state back from a relatively lower specific resistance crystalline state back to a relatively higher specific resistance amorphous state). However, the relatively high reset current may raise power consumption of the phase-change memory device and accelerate deterioration of the phase-change layer 53. Furthermore, because the temperature distribution Td leans toward the contact 51, temperature difference between the phase-change layer 53 and the contact 51 increases so that the phase-change layer 53 may detach from the contact 51.